Method of making contact electrodes to silicon gate, and source and drain regions, of a semiconductor device

ABSTRACT

In the fabrication of a metal oxide semiconductor field effect transistor (MOSFET) or of a metal gate field effect transistor (MESFET), characterized by a polycrystalline silicon gate (13) and a short channel of about a micron or less, a sequence of steps is used involving the simultaneous formation of source, drain, and gate electrode contacts by a bombardment with a transition metal, such as platinum, which forms metal-silicide layers (19, 21, 18) on the source and drain regions (10.1, 10.2) as well as the silicon gate electrode (13).

.Iadd.This application is a continuation, of application Ser. No.641,849, filed Aug. 17, 1984, which was a reissue of U.S. Pat. No.4,343,082, dated Aug. 10, 1982. .Iaddend.

FIELD OF THE INVENTION

This invention relates to the field of semiconductor apparatus, and moreparticularly to short channel field effect transistors and methods formaking them.

BACKGROUND OF THE INVENTION

It has been recognized by workers in the art of metal oxidesemiconductor field effect transistor (MOSFET) structures that a shallowsource or drain diffusion (small junction depth) can yield desirabledevice characteristics. For example, in an article by R. Hori et al.entitled "Short Channel MOS-IC Based on Accurate Two-Dimensional DeviceDesign", published in Supplement to Japanese Journal of Applied Physics,Vol. 15, pp. 193-199 (1976), it was recognized that relatively shallowsource and drain junction depths could help yield a relatively lowthreshold voltage shift in a short-channel MOSFET structure as well as arelatively high punch-through breakdown voltage. By "short-channel" ismeant a source to drain separation of less than about 2 microns.Short-channel MOSFET structures are desirable from the standpoint ofhigh frequency operation (of the order of 1 GHz) and miniaturization ofsize, particularly in very large scale integration of varioussemiconductor circuits, such as in a memory array in which each memorycell contains such a short-channel MOSFET.

A short-channel MOSFET made by conventional techniques suffers fromundesirable device properties stemming from a relatively high parasiticcapacitance between the polycrystalline silicon ("polysilicon") gateelectrode and the source or drain (or both). Similarly, a conventionallyfabricated short-channel metal gate (Schottky barrier) field effecttransistor (MESFET) device structure suffers from the problem ofundesirably high ohmic resistance along a path from source or drainelectrode (or both) to the conducting portion of the channel duringoperation in the ON state of the device. It would, therefore, bedesirable to have a method for making short-channel transistorsalleviating these problems.

SUMMARY OF THE INVENTION

In order to fabricate a short-channel polysilicon gate transistor, withlow parasitic characteristics, platinum silicide electrode contacts (15,16, 17) to the gate and source and drain are formed during a bombardmentwith platinum (FIG. 4) of the then exposed surfaces of the polysilicongate, the source, and the drain. Instead of platinum, other transitionmetals can be used which form a metal-silicide. At the time of thisbombardment, the side edge surface--but not the top surface--of thepolysilicon gate has advantageously been previously coated with asilicon dioxide layer (14). The parameters controlling this platinumbombardment are adjusted so that while platinum silicide is beingproduced on the exposed surfaces of the polysilicon gate, the source,and the drain--all of which are of silicon--neither any platinum norplatinum silicide accumulates on the exposed surface of the silicondioxide layer 14. Likewise, during this platinum bombardment, neitherplatinum nor platinum silicide accumulates on any other exposed silicondioxide layer (11) may have been previously formed as for the purpose ofdevice isolation.

This invention thus involves a method for making a transistor device ina silicon semiconductor body (10), said device (20, or 30, FIG. 6 orFIG. 7) having a gate electrode layer contact (15) to a polycrystallinesilicon gate electrode (13) during a stage of manufacture of saiddevice, a source electrode layer contact (16), and a drain electrodelayer contact (17), characterized in that subsequent to formation ofsaid polycrystalline gate electrode (13) with its side edges coated by asilicon dioxide layer (14), said gate and source and drain electrodecontacts (15, 16, 17) are all simultaneously formed by a bombardment ofbody (10) with a transition metal capable of forming a silicide whilethe body (10) is being subjected to applied electrical voltage (E₂, FIG.4) of such strength and frequency that silicide of said metal isproduced at a pair of then exposed regions (10.1, 10.2) contiguous witha major surface of the body (10) to form said source and drain electrodecontacts (16, 17) and that said silicide is produced during suchbombardment at the then exposed regions of the polycrystalline silicongate electrode (1) to form said gate electrode contact (15), and thatessentially no silicide accumulates on the silicon dioxide coating (14).Any metal that accumulates on this oxide can then be removed byconventional etching. The bombardment with the metal can be accomplishedby sputtering the metal from a target (31) of said metal.

The device structures that can be fabricated with the method of thisinvention include field effect transistor structures of the insulatedgate (FIG. 6) or conductive gate (FIG. 7) of the Schottky barrier orjunction field effect type.

BRIEF DESCRIPTION OF THE DRAWINGS

This invention, together with its features, objects, and advantages, maybe better understood from the following detailed description when readin conjunction with drawings in which:

FIGS. 1-6 illustrate in cross section a sequence of various stages inthe fabrication of a transistor device, specifically a MOSFET, inaccordance with a specific embodiment of the invention; and

FIG. 7 illustrates in cross section the final stage of anothertransistor device, specifically a MESFET, in accordance with anotherspecific embodiment of the invention.

Only for the sake of clarity, none of the drawings is to any scale.

DETAILED DESCRIPTION

As shown in the sequence of drawings, FIGS. 1-6, a short-channel MOSFETdevice 20 (FIG. 6) can be fabricated, in accordance with the invention,on a top major surface of a monocrystalline semiconductive silicon body10. As shown in the art of semiconductor multiple device fabrication("batch techniques"), many similar MOSFET devices can be simultaneouslyfabricated in such a body, all of these devices being mutuallyelectrically isolated by relatively thick ("field") oxide region 11.

The body 10 is formed by a single crystal semiconductor bulk portion 9upon a major planar surface of which has been grown an epitaxialsemiconductor layer 10.5. Typically, the semiconductor 9 is π-typeconductivity silicon; that is, having a relative low P-typeconductivity, for example, a bulk conductivity of about 10 ohm cm. Theepitaxial layer 10.5 is advantageously of moderate electricalconductivity, typically P-type, owing to a net significant acceptorimpurity concentration ordinarily of the order of about 10¹⁵ to 10¹⁷ percm³, typically about 10¹⁶ per cm³. The thickness of this epitaxial layeris typically about one or two micron or less.

In order to fabricate the MOSFET device 20 (FIG. 6), a thin ("gateoxide") silicon dioxide layer 12 (FIG. 1) is thermally grown on theexposed portion of the top surface of the body 10 typically to athickness of about a few hundred angstrom. Either before or after theformation of this thin oxide layer, relatively thick oxide regions 11are embedded, by means of a conventional thermal oxidation process, atselected portions of the epitaxial P layer down to the underlying π-typeoriginal crystal, in order to provide conventional oxide isolationbetween neighboring devices. It should be understood that electron beamor x-ray lithography, as well as photolithography, can be used incombination with standard resist masks to define the areas of selectiveformation of the thick oxide. Then an electrically conductive N-typepolycrystalline silicon layer 13' is deposited on a pre-selected area ofthe exposed surface of the thin oxide as formed by conventional resistmasking and etching techniques applied to a polycrystalline layeroriginally deposited all over the top surface, using lithography(electron beam, x-ray, or photo) techniques to shape the mask. Thispolycrystalline layer 13' is typically N-type semiconductor owing to itsbeing doped with significant donor impurities--such as arsenic--toincrease its electrical conductivity, and it has a length of typicallyabout 1.0 micron in the direction of the source to drain channel of thecompleted device and a width of typically a few microns in thetransverse direction thereto. This polysilicon layer is thus useful asthe gate electrode of the completed transistor device.

Next, the exposed top and side surfaces of the polycrystalline siliconlayer 13' are subjected to a conventional oxidation technique, whichoxidizes the polycrystalline silicon to yield a thin silicon dioxidecoating layer 1 on the surfaces of the thus remaining, unoxidized N-typepolycrystalline layer 13 (FIG. 2). Typically, this oxide coating 14 hasa thickness of about 500 angstrom. As a result of this oxidation of thepolycrystalline layer, the thickness of the original oxide layer 12(FIG. 1) is increased somewhat, as indicated by oxide layer 12' (FIG.2).

Then, the exposed portion of the thin oxide layer 12' and the topportion (but not side portions) of the thin oxide layer 14 are removed(FIG. 3) by an anisotropic etching technique, such as chemicallyreactive back-sputtering (reactive ion etching) with fluoride ions (F⁺)in a plasma produced by CHF₃. By "anisotropic[ etching it is meantetching preferentially in the direction perpendicular to the majorsurface of the body 10. For example, a cathode plate 32, typically ofplatinum, is located at a distance typically of several inches from thebody 10 in an evacuated chamber (not shown). This body is mounted on anelectrically conducting plane (not shown) connected through a capacitorC to an RF voltage source E, typically about 500 volts peak to peak at afrequency in the range of about 200 KHz to 14 MHz, typically 13.5 MHz.The pressure in the chamber is reduced to below about 1 mm Hg, typicallyabout 50 micron Hg, in order that, while a plasma forms in theneighborhood of the cathode plate 32, the top surface of the epitaxiallayer 10.5 remains inside a dark space region of the discharge from thecathode plate 32. The RF power is typically about 20 to 100 watts for acathode several inches in diameter, and the temperature of the body ismaintained at typically about 500° C. In this manner, the fluoride ionsbombarding any element (including the oxide and polysilicon layer)located at the top surface of the body 10 strike it from a directionwhich is essentially normal to the top major surface of the epitaxiallayer 10.5; thereby these ions completely remove the thin oxide only atthe surface portions where the normal to the surface is parallel to thevelocity vector of the bombarding ion, but not at the side portions. Inso removing the thin oxide portions, however, it is important that theside surfaces of the polysilicon layer 13 thus remain coated with thethus remaining (sidewall) portions of the oxide layer 14. The thickness(in the horizontal direction) of this remaining sidewall oxide istypically about 500 angstrom, and is in any event advantageously equalto, or less than, approximately the Debye length in the silicon in theregion of the source-channel interface of the ultimately completeddevice.

Next, as indicated in FIG. 4, positively charged argon ions are directedupon a platinum cathode target 31 in order to sputter platinum from thetarget onto the body 10. These positive argon ions have suitable kineticenergies due to an accelerating voltage E₁ (of negative polarity)applied to the target. This sputtering of platinum results in thearrival of platinum atoms and/or platinum ions at the exposed topsurface of the epitaxial layer 10.5 where the platinum accumulates onthe exposed silicon as metal-like platinum silicide electrode layers 15,16 and 17. The voltages E₁ and E₂ are adjusted so that the removal rateof platinum from the exposed oxide portions of the top surface isgreater than the arrival rate. Thus, essentially no metal or metal-likesubstance of any kind (platinum or platinum silicide) accumulates on anyportion of exposed oxide, either the field oxide or the gate oxide.However, if any metal should accumulate on the oxide, a subsequenttreatment with a conventional etching solution, as aqua regia, can beused to remove this metal but not the silicide or oxide layers.

The donor impurity dopant arsenic or antimony (or both) canadvantageously be added to the target 31 for the purpose ofsimultaneously forming by "co-sputtering" a pair of spaced apart,self-aligned N+ zones 10.1 and 10.2 during the bombardment withplatinum. These N+ zones are formed by rejection from the platinumsilicide of the impurity dopant into the silicon ("segregationcoefficient"). Because all subsequent processing temperatures are wellbelow the temperature at which significant diffusion of impurities insilicon occurs, the depth of the resulting N+ P junctions in the silicon(beyond the platinum silicide) can be as little as 100 angstrom or less.

Alternatively, the N+ zones 10.1 and 10.2 can be formed at an earlierstage of the fabrication--for example, by means of conventionaltechniques as ion implantation and diffusion of donor impurities usingthe polycrystalline layer 13 with sidewall oxide 14 as a mask which isimpervious to these impurities.

Typical values of the parameters useful for this platinum bombardmentstep are: E₁ is a D.C. voltage equal to about 1000 volts, and E₂ is anRF voltage in the range of typically about 500 to 1000 volts peak topeak at a frequency of about 13 MHz. The RF power is typically about 20to 100 watts for a cathode 31 of several inches in diameter. Thefrequency and amplitude of E₂ control the removal rate of platinum andplatinum silicide during the bombardment. The fact that the removal rateof platinum is thus made to be about two or more times that of platinumsilicide tends to ensure the net removal of any metallic platinuminitially arriving on the exposed oxide while the net permanentformation and accumulation of platinum silicide occurs on the exposedsilicon (whether monocrystalline or polycrystalline). The temperature ofthe body 10 during this sputtering process is typically about 625° C.,while the ambient pressure of argon is typically about 10 to 20 micronHg.

After the formation of the platinum silicide layers 15, 16 and 17 on theexposed silicon surfaces to a thickness of typically about a fewhundered angstrom, the top surface of the body 10 is coated at selectedareas with an insulating layer 22 (FIG. 5) by conventional deposition,masking, and etching techniques. This layer 22 is typicallytetra-ethyl-ortho-silicate having a thickness of, for example, about5000 angstrom. By conventional techniques, metallization such asaluminum is then applied through apertures in the layer 22 to contactthe platinum silicide layers 15, 16, and 17, in order to form therespective electrode metallization contacts 18, 19, and 21 for the gate,source, and drain, respectively, of the completed MOSFET device 20 (FIG.6).

It should be noted that during operation, a back-gate (substrate) biasvoltage of magnitude two volts or more is desirable, in order to preventshort circuits of different devices due to surface channels under thethick (field) oxide. Alternatively, such channels can be avoided byusing a v-type (low conductivity N-type) body 10.

For good transistor device performance, it is useful to have the sourceand drain regions 10.1 and 10.2 as shallow as possible; that is, theimplantation process for these regions should limit their depths beneaththe surface of the semiconductor body to a value of about a few hundredangstrom, which can be achieved by using a semiconductor bodytemperature of no greater than 500° C. during any fabrication stepsubsequent to the diffusion of these N+ zones.

As illustrated in FIG. 7, the growth of the thin oxide layer 12 can becompletely omitted, so that the N-type polycrystalline silicon layer 13directly contacts the top surface of the silicon semiconductor body 10,thereby forming a PN junction thereat. The resulting device 30 is thusan equivalent of a junction FET device, ("JFET"). In this device (FIG.7), the N+ regions 10.1 and 10.2 advantageously are replaced by P+regions 31.1 and 31.2, respectively, so that the device has a relativelylow barrier Schottky source and a relatively low barrier Schottky drain;for example, a barrier of 0.25 volts in the case of platinum silicide onP-type silicon. Conversely, on this P-type silicon, a relatively highSchottky barrier of about 0.65 volt is formed by hafnium, for example.

The distance between drain and gate can be made larger than that betweensource and gate, by locating the electrode 17 farther away from thepolysilicon layer 13, so that this electrode does not directlyphysically contact the oxide layer 14, in order to provide a longerdrift region in the neighborhood of the drain. On the other hand, the P+regions 31.1 or 31.2 (or both) can be omitted in the device illustratedin FIG. 7. Also, care must be taken that the diffusion of these regions31.1 and 31.2 does not extend either of these regions laterally to thepolycrystalline layer 13; otherwise, an undesirable short circuit of thegate electrode to source or drain (or both) will occur.

Moreover, again omitting the thin oxide layer 12, a metal gate FET("MESFET") structure can be obtained by carrying out the metalbombardment step (FIG. 4) for sufficiently long a time that thepolycrystalline layer 13 is complete converted to metal-silicide. Insuch a case it is advantageous to use a relatively high barrier Schottkymetal such as hafnium for the P-type silicon layer 10.5 (platinum forN-type silicon), advantageously together with a pair of localizeddiffused P+ type zones instead of the localized N+ zones 10.1 and 10.2in the P-type silicon layer 10.5 (or to retain the localized N+ zones10.1 and 10.2 but in an N-type epitaxial layer instead of the P-typelayer 10.5). Again, each (or both) of the localized diffused zones canbe omitted (especially at the source region), whereby the source or(and) the drain can be of the Schottky barrier type.

Instead of growing the epitaxial P-type layer 10.5, the top surface ofthe original π-type semiconductor base 9 can be treated with excessacceptor impurities. This π-type base 9 contains about 10¹⁶ per cm³excess significant acceptor impurities. In an example, solely forillustrative purposes, upon the top surface of the original π-type base9 are successively formed a 350 angstrom thermally grown layer ofsilicon dioxide and a 1200 angstrom layer of silicon nitride. Using aphoto or x-ray or electron beam resist material as a mask, the siliconnitride layer is removed from the areas where the thick isolation oxideis to be formed; that is, the nitride layer is removed only in thecomplement of the GASAD (gate and source and drain) areas. Leaving theresist in place as an impervious mask against ion implantation, achannel ("chan") stop is formed by implanting boron ions of typicallyabout 100 kev to a dose of typically about 10¹² to 10¹³ per squarecentimeter in the complement of the GASAD areas. Then, the resistmaterial is removed, leaving the nitride layer in place; and a thick9000 angstrom field oxide layer is thermally grown in the field oxideareas (complement of the GASAD areas) while the top portion of thenitride layerin the GASAD areas is converted into an oxynitride layer.Next, successively using etching solutions of buffered hydrofluoric acidand phosphoric acid, the oxynitride and nitride layers, respectively,are successively removed from the GASAD areas while only a smallfraction of the oxide layer is thereby removed from the thick fieldoxide layer. Then, thermal growth produces a total of 3000 angstrom ofsilicon dioxide in the GASAD areas and a total of about 9500 angstrom ofsilicon dioxide in the field oxide area. Next, all the oxide in theGASAD areas is removed by etching with buffered hydrofluoric acid, whilethe field oxide thickness is reduced to about 6500 angstrom. Thenanother thermal growth step produces a layer of silicon dioxide in theGASAD areas having a thickness in the range of about 100 to 500angstrom, typically 125 angstrom. Next, boron ions are implanted with 35kev energy, sufficient to penetrate to the underlying silicon only inthe GASAD areas, to a dose of 2×10¹² boron ions per square centimeter,in order to provide a convenient operating threshold voltage in theultimate transistor devices of the enhancement mode type. If depletionmode devices are also to be formed at some of the GASAD areas, then aresist material is applied to these areas prior to the 35 kev boron ionimplantation. This resist is then removed after this boron implantation,next, the oxide is completely removed from all the GASAD areas (a smallfraction from the field oxide areas); and finally the oxide layer 12(FIG. 1) is thermally grown. Although the invention has been describedin terms of specific embodiments, various modifications can be madewithout departing from the scope of the invention. For example, thesemiconductor base 9 can be v-type (low conductivity N-type) instead ofπ-type. Moreover, N-type and P-type conductivity can be everywhereinterchanged in all the above-described devices.

Instead of using fluoride ions to remove the oxide (FIG. 3), other ions,such as argon, may be used; that is, either a chemically reactive ornonreactive ion etching may be used for the oxide removal step.Moreover, instead of platinum, other transition metals methods can beused, such as cobalt, hafnium, titanium, or tantalum, for example, eachof which forms a metal-silicide suitable for a Schottky barrier onsilicon. Moreover, the N+ region 10.1 or 10.2 (or both) can also beomitted from the device shown in FIG. 6, thereby forming a Schottkybarrier source or drain (or both) in a MOSFET structure. Instead offorming the platinum silicide by sputtering, platinum itself can firstbe evaporated all over the surface and then be converted into platinumsilicide by means of a temperature "spike" treatment typically of about400° to 650° C. for typically about 2 to 6 minutes; the platinumremaining as such or the oxide can thereafter be removed by etching withhot aqua regia.

We claim:
 1. A method for making transistor devices in a siliconsemiconductor body (10), each said device (20 or 30, FIG. 6 or FIG. 7)having a gate electrode layer contact (15) to a polycrystalline silicongate electrode (13) during a stage of manufacture of said device, asource electrode layer contact (16), and a drain electrode layer contact(17), including the steps of coating side edges of said polysilicon gateelectrode (13) with a silicon dioxide layer (14), and forming said gateand source and drain electrode contacts simultaneously by .[.depositingon.]. .Iadd.bombarding .Iaddend.said body (10) .Iadd.with .Iaddend.atransition metal capable of forming a silicide to form.Iadd., during thebombarding, .Iaddend.silicide of said metal contacting a pair of thenexposed regions (10.1, 10.2) contiguous with a major surface of the body(10), thereby to form said source and drain electrode contacts (16, 17),and simultaneously to form said silicide contacting the then exposedregions of the polycrystalline silicon gate electrode (13), thereby toform said gate electrode contact (15), whereby essentially no silicideaccumulates on the silicon dioxide coating (14).
 2. The method of claim1 in which said step of forming comprises bombardment of said body withsaid transition metal while said body is being subjected to an appliedelectrical voltage (E₂) of predetermined strength and frequency, wherebyessentially no .Iadd.metal or metal.Iaddend.-silicide accumulates on anexposed surface of an oxide region (11) isolating said device from itsneighbor in a multiplicity of such devices formed simultaneously in saidbody.
 3. The method of claim 1 .[.or 2.]. including the further step ofremoving by etching any of said metal that accumulates on said silicondioxide coating (14).
 4. The method of claims 1 or 2 in which the stepof forming is continued until the gate electrode layer (15) contacts thesemiconductor body (10).
 5. The method for making semiconductorapparatus comprising the steps of:(a) forming a polycrystalline siliconlayer covering a first silicon dioxide layer which coats a first portionof a major surface of a silicon semiconductor body; (b) forming a secondsilicon dioxide layer on an exposed side edge of the polycrystallinesilicon layer, leaving a major surface of a polycrystalline layerexposed and free of silicon dioxide; (c) subjecting the body to abombardment with a metal, which forms metal-silicide, from a target ofsaid metal under the influence of predetermined voltage applied to saidbody whereby layers of metal-silicide are formed.Iadd., during thebombardment, .Iaddend.at the exposed portions of the major surfaces ofthe semiconductor body and of the polycrystalline silicon layer andwhereby essentially no .Iadd.metal or .Iaddend.metal-silicide is formedon any portion of the second silicon dioxide layer during thebombardment.
 6. The method of claim 5 in which the metal is platinum,hafnium, cobalt, tantalum, or titanium.
 7. A method for makingsemiconductor apparatus comprising the steps of:(a) forming apolycrystalline silicon layer on a selected portion of a major surfaceof a semiconductor silicon crystal body; (b) forming a second silicondioxide layer on an exposed side edge of the polycrystalline siliconlayer, leaving a major surface of a polycrystalline layer exposed andfree of oxide; (c) subjecting the body to a bombardment with atransition metal capable of forming metal-silicide under the influenceof voltage applied to said body such that layers of said silicide areformed.Iadd., during the bombardment, .Iaddend.at the exposed portionsof the major surfaces of the semiconductor body and of thepolycrystalline silicon layer and that no .Iadd.metal or.Iaddend.metal-silicide is formed on any portion of the second silicondioxide layer during the bombardment.
 8. The method of claims 6 or 7 inwhich said bombardment with metal is produced by sputtering from atarget of said metal upon which ions of suitable kinetic energy areincident.
 9. The method of claims 6 or 7 in which an oxide isolationlayer of greater thickness than the first silicon dioxide layer isembedded in a second, separate portion of the major surface of thesilicon body prior to the step of subjecting the body to thebombardment, whereby no .Iadd.metal or .Iaddend.metal-silicide is formedon any portion of the oxide isolation layer.
 10. The method of claim 9in which the metal is platinum or hafnium.